The present invention relates generally to memory cell margin testing, and more particularly to testing sense amplifier operability in conjunction with an array of dynamic cell plate sensed memory cells.
Memory devices comprise an array of memory cells. Wordlines (row lines) and digitlines (column lines or bitlines) are employed to access memory cells of a memory array.
In a conventional memory array, for a read operation digitlines are electrically disconnected from a bias voltage and allowed to float. The digitlines remain for a sufficient time at a precharge voltage owing to their capacitance. Voltage on a wordline is then increased to digitline precharge voltage plus at least a threshold voltage amount to access a memory cell. Once accessed, a memory cell capacitor begins to discharge onto an associated digitline, in which case digitline voltage on the accessed line is either increased or decreased depending on the presence or absence of charge stored in the accessed memory cell. This change in voltage, owing to charge sharing, is conventionally compared against a reference digitline floating at the precharge voltage.
After a memory cell is accessed, sensing the voltage differential is sensed. Digitlines are connected to a sense amplifier for sensing a voltage difference between two digitlines, namely, the digitline accessed and its reference line. However, as voltage logic levels are decreased owing to decreases in memory cell size, voltage swings are reduced accordingly. A smaller voltage swing, in combination with transistor threshold voltages, renders sense amplifiers voltage margin limited.
To address lower voltage levels, an architecture has been proposed, which has been referred to as xe2x80x9cdynamic cell plate sensingxe2x80x9d or xe2x80x9cDCPS.xe2x80x9d In a DCPS array, a plate line is connected to a memory cell""s capacitor cell plate. Plate lines and associated digitlines are maintained at a precharge voltage level (e.g., Vcc/2) prior to a read operation. For a read operation, these lines are allowed to float just prior to wordline firing. Voltages on an accessed digitline and its associated plate line move in opposite directions owing to cell capacitor charges moving in opposite directions when accessed. This provides for a larger voltage swing for sensing operations.
Conventional margin testing of a DCPS cell of necessity tests voltage movement of both the accessed digitline and its associated plate line. However, it would be desirable to provide a cell margin test which tests voltage movement on an individual digitline or plate line against a reference potential to provide a more accurate indication of margin. Such a test would provide a better indication of cell margin limitations on each line.
The present invention provides a method for testing cell margin for a memory cell in a dynamic cell plate sensing array architecture. For cell margin testing, memory cell charge transfer (including either charge addition or depletion) to a digitline or plate line takes place. Prior to charge transfer, an isolation device is turned off to selectively isolate either a digitline or a plate line associated with the accessed memory cell. The selected digitline or plate line is isolated from a sense amplifier. The non-selected line is coupled to the sense amplifier during memory cell charge transfer. This results in voltage movement or swing at a sense amplifier sense node in electrical communication with the accessed memory cell and no, or no significant, voltage movement at another sense amplifier sense node not in electrical communication with the accessed memory cell. The isolated sense node thus floats at an equilibrate potential. Consequently, a voltage difference is created between the two sense amplifier nodes, permitting cell margin testing for sense amplifier latching with respect to voltage movement on either a plate line or a digitline.
Therefore, the present invention provides cell margin testing of a memory cell in a DCPS array architecture on one of two lines at a time, namely, either a cell plate line or a digitline. Moreover, because voltage movement occurs at only one sense node of a sense amplifier and an opposite sense node stays at or near a reference potential, a direct comparison of sense amplifier operation data in a DCPS environment may be made with data from a sense amplifier operating in a non-DCPS environment.